----------------------------------------------------------------
-- Test Bench for D flip-flop
----------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity tb_2bits is		-- entity declaration
end tb_2bits;

----------------------------------------------------------------

architecture TB of tb_2bits is

    signal T_data: 	std_logic;
    signal T_clock:	std_logic;
    signal T_rwa:	std_logic;
    signal T_rwb:	std_logic;
    signal T_ea:	std_logic;
    signal T_eb:	std_logic;
	
    component cmp_2bits
    port(	data:	inout std_logic;
    		rwa:	in std_logic;   		
    		rwb:	in std_logic;
    		ea:		in std_logic;
    		eb:		in std_logic;
            clock:	in std_logic
    );
    end component;
		
begin

    U_DFF: cmp_2bits port map (T_data, T_rwa, T_rwb, T_ea, T_eb, T_clock);

    -- concurrent process to offer clock signal	
    process
    begin
	T_clock <= '0';
	wait for 5 ns;
	T_clock <= '1';
	wait for 5 ns;
    end process;
	
    process

	variable err_cnt: integer := 0; 

    begin
	
    -- escribo 1 en el bit A
    T_ea <= '1';
    T_eb <= '0';
    T_data <= '1';
    T_rwa <= '1';
    wait for 12 ns;

    assert (T_data='1') report "Error 1!" severity error;

    -- escribo 0 en el bit B
    T_ea <= '0'; 
    wait for 10 ps;
    T_eb <= '1';
    wait for 10 ps;
    T_data <= '0';
    wait for 10 ps;
    T_rwb <= '1';
    wait for 4 ns;

    assert (T_data='0') report "Error 2!" severity error;

    -- chequeo que A se haya guardado bien

    T_ea <= '1';
    T_eb <= '0';
    T_rwa <= '0';
    wait for 10 ns;

    assert (T_data='1') report "Error 3!" severity error;

    -- chequeo que B se haya guardado bien

    T_ea <= '0';
    T_eb <= '1';
    T_rwb <= '0';
    wait for 10 ns;

    assert (T_data='0') report "Error 4!" severity error;

    -- copio de A a B

    T_ea <= '1';
    T_eb <= '1';
    T_rwa <= '0';
    T_rwb <= '1';
    wait for 10 ns;

    assert (T_data='1') report "Error 5!" severity error;

    -- verifico que haya copiado bien en B

    T_ea <= '0';
    T_eb <= '1';
    T_rwb <= '0';
    wait for 10 ns;

    assert (T_data='0') report "Error 6!" severity error;

	wait;

    end process;

end TB;

-----------------------------------------------------------------
configuration CFG_TB of tb_2bits is
	for TB
	end for;
end CFG_TB;
-----------------------------------------------------------------

